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Plasma Applications Group - Announcements

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Topic: Material Opportunities for Semiconductors

Meeting Date: September 25, 2014
Start Time: 2:00 - 5:00 pm


SEMI Global Headquarters
Seminar rooms 1 & 2
3081 Zanker Road
San Jose, CA 95134
**Park in SEMI Global Parking Lots ONLY**


Roman Mostovoy, AMAT,
Jeffrey Shields, Adesto Technologies,


2:00 - 2:30 Material Challenges for EUV,
-Patrick Naulleau, Director, Senior Staff Scientist, Center for X-Ray Optics, Lawrence Berkeley National Laboratory
Abstract: The introduction of extreme ultraviolet lithography (EUV) has raised a host of new materials challenges for the semiconductor industry. These challenges cover nearly every aspect of lithography and in this presentation we will cover the topics of photoresists, masks, and optics. Reducing the wavelength to 13.5 nm significantly changes the radiation chemistry and raises concerns about shot noise and high near-normal reflectivity at EUV wavelengths requires extremely accurate nano multilayers to be produced with roughnesses below the 50 pm level.

Biography: Patrick Naulleau received his B.S. and M.S. degrees in electrical engineering from the Rochester Institute of Technology, Rochester, NY, in 1991 and 1993, respectively. He received his Ph.D. in electrical engineering from the University of Michigan, Ann Arbor in 1997 having performed his dissertation work in the areas of optical signal processing and coherence theory. In 1997 Dr. Naulleau joined Lawrence Berkeley National Laboratory as a staff scientist where he has focused his research on advanced EUV lithography and metrology. From June 2005 through March 2008, Dr. Naulleau additionally joined the faculty at the University at Albany, SUNY as Associate Professor, also concentrating in the area of EUV lithography. In April 2010 Dr. Naulleau took the position of Director of the Center for X-ray Optic at Lawrence Berkeley National Laboratory. Dr. Naulleau has over 300 publications in the field as well as 19 Patents.

2:30 - 3:00 Tuning the threshold voltage of carbon nanotube transistors for flexible, CMOS circuit,
-Evan Wang, PhD, Department of Materials Science and Engineering at Stanford University.

Abstract: Tuning threshold voltage of a transistor is crucial for realizing robust digital circuits. For Silicon transistors, the threshold voltage can be accurately controlled by doping, mainly through ion implantation. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors (TFTs). Here, we report a method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either vacuum evaporation or solution coating. The threshold voltages of our polythiophene-sorted SWNTs TFTs can be continuously tuned over a wide range. Photoelectron spectroscopy (PES) measurements confirmed that the SWNT Fermi energy decreased with increased doping concentration. Utilizing this approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented high noise margin of 28V at VDD = 80V (70% of 1/2VDD) and a gain of 85. Additionally, equally robust SWNT CMOS inverters (noise margin 72% of 1/2VDD), NAND and NOR logic gates with rail-to-rail output voltage swing and sub-nanowatts power consumption were fabricated onto a highly flexible substrate for the first time.

Biography: Huiliang (Evan) Wang is a 4th year PhD student in Department of Materials Science and Engineering at Stanford University. He is working on polymer sorting of carbon nanotubes and their application in flexible circuit with Prof Zhenan Bao. He published first-author papers in journals such as PNAS, Advanced Materials and ACS Nano (x3). He did his undergraduate degree in Materials Science at University of Oxford before he came to Stanford. Personal Website:

3:00 - 3:30 Low-Power Resistive Memory with 1D and 2D Electrodes,
-Feng Xiong, Ph.D. Stanford Pop Lab (EE) and Cui Lab (MSE)
Abstract: A central issue of nanoelectronics concerns their fundamental scaling limits, that is, the smallest and most energy-efficient devices that can function reliably. Unlike charge-based electronics, memory devices based on phase change materials (PCMs) and metal oxides (RRAM) are more immune to leakage at nanoscale dimensions. In order to probe the scalability of these materials, we developed novel approaches to build PCM nanowires and RRAM crossbars with individual carbon nanotube (CNT) electrodes. With diameters ranging from 1-5 nm, CNTs are the smallest electrodes available. By utilizing CNTs in this context, we are able to reduce the programming current and power of such memory devices by more than 100× compared to state-of-the-art. We have also demonstrated data storage with graphene electrodes and are examining the benefits of integrating RRAM with other 2D materials such as MoS2.

Biography: Feng Xiong is currently a Postdoctoral Fellow at Stanford University, working with Prof. Eric Pop (EE) and Prof. Yi Cui (MSE). He received his M.S. and Ph. D. degree in electrical engineering (EE) from the University of Illinois at Urbana-Champaign (UIUC) in 2010 and 2014, his B.Eng. in EE from National University of Singapore (NUS) in 2008. His research interests include low-dimensional materials for nanoelectronics and memory applications. His doctoral thesis was on scaling study of phase change memory using carbon nanotube electrodes. He received several awards including the Nano- and Quantum Science and Engineering Postdoctoral Fellowship, MRS Graduate Student Gold award and TSMC Outstanding Student Research Gold Award. He is a member of IEEE and MRS. More information can be found online at

3:30 - 3:45 Break

3:45 - 4:15 Carbon Nanotube Vias for End-of-Roadmap On-chip Interconnects,
-Cary Y. Yang, Professor, Electrical Engineering Department, Center for Nanostructures, Santa Clara University, Santa Clara, CA.

Abstract: As the silicon integrated circuit (IC) technology node continues to scale down in the sub-30 nm regime, new structures and materials are required for front and back-end devices, since existing materials cannot keep up with the desirable IC or chip performance and reliability. Currently, copper is the industry-standard material used to connect devices across the chip. However, the aggressive scaling of the interconnect linewidth leads to the current density within Cu lines fast approaching its limit of ~1MA/cm2, and resulting in reliability problems due to electromigration. Thus, new materials with higher current-carrying capacities than Cu such as carbon nanotubes (CNTs) and graphene are needed. Although nanocarbons have electrical and mechanical properties superior to those of Cu, there are major challenges which must be overcome before they can be considered serious contenders to replace Cu as the interconnect materials in the end-of-roadmap domain. The singularly critical challenge for CNT via interconnects is optimizing carrier transport across the CNT-metal interface, or simply stated, minimizing the contact resistance. To meet this challenge, we have fabricated via test structures from 1000 nm down to 60 nm in diameter using conventional silicon process technology, and grown vertical CNT arrays inside these vias using PECVD. Electrical measurements are performed on individual vias as well as on single CNTs inside using a nanoprober. Contact resistance for via or individual CNT is extracted from measured total resistances for various via or CNT heights, respectively. The results on CNT array areal density and contact resistance allow us to assess the total via resistance trend as linewidth decreases, and to project electrical performance for vias with diameters 30 nm and beyond. Further, such projections are then compared with resistances of Cu vias with similar linewidths, which in turn provide a realistic assessment of CNT via interconnects for potential applications in end-of-roadmap IC technology nodes.

Biography: Cary Y. Yang received the B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Pennsylvania. After working at M.I.T., NASA Ames Research Center, and Stanford University on electronic properties of nanostructure surfaces and interfaces, he founded Surface Analytic Research, a Silicon Valley company focusing on sponsored research projects covering various applications of surfaces and nanostructures. He joined Santa Clara University in 1983 and is currently Professor of Electrical Engineering and Director of TENT Laboratory. He was the Founding Director of Microelectronics Laboratory and Center for Nanostructures, and served as Chair of Electrical Engineering and Associate Dean of Engineering at Santa Clara. His research spans from silicon-based nanoelectronics to nanostructure interfaces in electronic, biological, energy-storage systems. An IEEE Fellow since 1999, he served as editor of the IEEE Transactions on Electron Devices, president of the IEEE Electron Devices Society, and elected member of the IEEE Board of Directors. He currently serves as Vice Chair of the IEEE Awards Board. In 2001, on behalf of the People to People Ambassadors Program, he led an Electron Devices Delegation to visit universities, government institutes, and companies in the People’s Republic of China. He was recognized with the 2004 IEEE Educational Activities Board Meritorious Achievement Award in Continuing Education "for extensive and innovative contributions to the continuing education of working professionals in the field of micro/nanoelectronics." In 2005, he received the IEEE Electron Devices Society Distinguished Service Award. He currently holds the Bao Yugang Chair Professorship at Zhejiang University in China.

4:15 - 4:45 Advantages and Challenges of FinFET Devices and Technologies,
-Jack C. Lee, Professor of the Electrical and Computer Engineering Department, The University of Texas at Austin.

Abstract: FinFET devices are used in CMOS integrated circuits in 22 nm technology node and beyond, because of its good leakage current / power dissipation characteristics and better scalability. However, there are still many issues and challenges such as threshold voltage control, width quantization and process variability. In this talk, the process integration technology and the device characteristics of FinFET will be discussed. We will also discuss the FinFET on bulk Si substrate (bulk-FinFET) versus FinFET on SOI substrate (SOI-FinFET) in terms of process complexity, fin shape, processing / wafer cost and variability.

Biography: Jack C. Lee is a Professor of the Electrical and Computer Engineering Department and holds the Cullen Trust for Higher Education Endowed Professorship in Engineering at The University of Texas at Austin. He received the B.S. and M.S. degrees in electrical engineering from University of California, Los Angeles, in 1980 and 1981, respectively; and the Ph.D. degree in electrical engineering from University of California, Berkeley, in 1988. From 1979 to 1984, he was a Member of Technical Staff at the TRW Microelectronics Center, CA, in the High-Speed Bipolar Device Program. In 1988, he joined the faculty of The University of Texas at Austin. His current research interests include semiconductor device (i.e. MOSFETs) fabrication processes, characterization and modeling, dielectric process, high-K gate dielectrics and electrode, semiconductor memory applications, and alternative channel materials. He has published over 500 journal publications and conference proceedings and several patents; and co-authored one book and two book chapters on high-K gate dielectrics. Dr. Lee is a Fellow of IEEE and a Distinguished Lecturer for the IEEE Electron Devices Society.

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