Plasma Applications Group - Announcements
(Formerly: Plasma Etch Users Group)

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Topic: Advances in Plasma Technology

Meeting Date: July 15, 2010
Meeting Time: 11:00 am - 3:00 pm

Agenda:

11:00-11:30 Observations on the business and market aspects of Tier 2 ($10M-$100M annual revenue) capital equipment companies working on plasma applications in the 300mm and sub-300mm space in the fields of LED, MEMS, and packaging,
-Robert Castellano, The Information Network
Abstract: TBD
Biography: Robert N. Castellano, PhD, is President of THE INFORMATION NETWORK, a leading consulting and market research firm for the semiconductor, LCD, HDD, and solar industries. Dr. Castellano is internationally recognized as one of the leading experts in these areas. He has nearly 25 years of expertise as an industry analyst. Dr. Castellano has provided insight on emerging technologies to many business and technical publications, including Business 2.0, BusinessWeek, The Economist, Forbes, Investor's Business Daily, Los Angeles Times Magazine, the New York Times, USA Today and the Wall Street Journal. He is a frequent speaker at conferences and corporate events. He has over ten years experience in the field of wafer fabrication at AT&T Bell Laboratories and Stanford University before founding The Information Network in 1985. He has been editor of the peer-reviewed Journal of Active and Passive Electronic Devices since 1985. He is author of the book "Technology Trends in VLSI Manufacturing" published by Gordon and Breach. His book "Solar Cell Processing" was published in 2009 by Old City Publishing. He received his Ph.D. in Solid State Chemistry from Oxford University (UK).

11:30-12:00 Plasma Activation – An Enabling Technology for Wafer Bonding,
-Eric F. Pabo, Viorel Dragoi, Thorsten Matthias, and Paul Lindner, EVGroup
Abstract: Plasma activation of wafers prior to wafer bonding has enabled several key advances in wafer bonding. The key improvements are the reduction of the thermal budget required during annealing to achieve a high strength bond and the ability to form an initial bond at room temperature. This reduction in thermal budget make the bonding process compatible with CMOS devices and most MEMS devices. In this presentation the basics of PA process and results along with process flows and product applications such as 3D will be reviewed.
Biography: Eric Pabo is the business development manager for MEMS for EV Group; previously he had been an applications engineer for bonding for EVGroup for 3.5 years. Prior to working for EVGroup he spent 5 years working on wafer level packaging and assembly processes for HP and Agilent Technologies. He has over 20 years experience in electronics manufacturing, is a professional engineer registered in the State of Colorado, is finishing his Six Sigma Black Belt Certification and earned a Bachelor’s Degree in Mechanical Engineer from Colorado State University.

12:00-12:30 Examining cost of ownership of crystalline-silicon solar-cell processing: texturization and cleaning,
-David Jimenez, Wright Williams & Kelly, Inc., Ismail Kashkoush, Ph.D., Akrion Systems
Abstract: This presentation examines the need for saw damage removal and the follow-on processes of pre-cleaning, texturization and cleaning. We further discuss the process considerations for wet and plasma approaches before taking a detailed look at texturization using random pyramid formation. The paper will conclude with a view of current and future wet process techniques and a cost of ownership (COO) case study using the Akrion Systems GAMA-Solar as an example.
Biography: Mr. David Jimenez is President and co-Founder of Wright Williams & Kelly, Inc., the largest privately held operational cost management software and consulting services company. He has approximately 30 years of industry experience including management positions with NV Philips and Ultratech Stepper. He holds a B.Sc. in Chemical Engineering from the University of California, Berkeley and an MBA in Finance. He was also responsible for the design of the semiconductor industry’s de facto standard in cost of ownership, TWO COOL® and holds a patent for his work on PRO COOL® for Wafer Sort & Final Test. His large scale program management experience includes SEMATECH’s cost of ownership commercialization, SEMATECH’s semiconductor equipment database, the United States Display Consortium’s (USDC) factory simulation program, Sandia National Labs factory cost model commercialization, and Ultratech Stepper’s scanner replacement development. He is a recipient of the Texas Instruments Supplier Excellence Award for his contributions to their cost reduction efforts. For nearly 20 years, he has been a facilitator in the SEMI sponsored workshop, “How to Successfully Manage New Product Introductions” and “Understanding and Using Cost of Ownership.” He is also the author of numerous articles in the fields of productivity and cost management.
Biography: Dr. Ismail Kashkoush is vice president of Technology at Akrion Systems. In his role, Dr. Kashkoush has responsibility for managing the company’s process engineering department and R&D programs, and also maintains the technology roadmap and provides technical leadership for product and process development. He holds 17 patents in the field of wafer surface preparation science and technology and has published and coauthored more than 65 articles in the area of microcontamination characterization, removal, and control. Dr. Kashkoush holds a Ph.D. in engineering sciences from Clarkson University, Potsdam, NY.

12:30-1:00 Laser Produced Plasma Light Sources for EUV Lithography, -Bruno La Fontaine, Cymer
Abstract: As the semiconductor industry continues its drive to manufacture integrated electronic devices with more and more functionalities, it needs to maintain its requirement for cost-effective technologies capable of patterning circuits with smaller and smaller dimensions. As such circuit patterns are being devised using design rules less than about 30 nm half-pitch, extreme ultraviolet (EUV) lithography is considered to be the leading candidate for patterning these circuits on silicon chips. The sources for EUV lithography need to meet very stringent requirements in terms of power (>100 W), lifetime and uptime. To achieve such performance, Cymer has been developing, testing and integrating several key source components. We present the latest results on high-power extreme-ultraviolet (EUV) light sources for lithography. This includes operation of high-power pulsed CO₂ lasers, high repetition-rate Sn droplet targets, and collection of EUV light using multilayer-coated optics.
Biography: At Cymer, Mr. La Fontaine is the Sr. Director of Global EUV applications, responsible for the successful application of EUV sources for lithography at chip manufacturers.
Mr. La Fontaine received a Ph.D. in laser-plasma physics from INRS in Canada, in 1992. In the early nineties, he worked on EUV lithography at AT&T Bell Labs and Lawrence Livermore National Labs. In the late nineties, he was a professor at INRS working on the applications of ultrashort pulse lasers. Between 2000 and 2010, he worked at AMD/GlobalFoundries leading their EUV lithography program. Mr. La Fontaine was a Fellow of AMD/GlobalFoundries and is a Fellow of SPIE.

1:00-1:30 Monolayer Etching using soft plasma sources,
-Ed Korczynski, BetaSights
Abstract: For volume manufacturing of semiconductors process tools generally require high-throughput, and so leading OEM plasma etchers are generally designed to maximize material removal rates. However, with Moore's Law and Denard Scaling having driven the industry to atomic device dimensions, there are new requirements for atomic-layer etch processes to match atomic-layer deposition (ALD) of specialized thin-films in today's ICs. In particular, high-k metal gate (HKMG) transistor fabrication requires the careful etch of mere monolayers of oxides, with gentle control needed more than raw power. Low power plasma sources based on planar slot antennas can etch monolayers at low electron temperatures, suitable for the fabrication of 32nm node ICs and beyond.
Biography: Ed Korczynski is the founder of BetaSights, an information consultancy tracking new process technology in IC, FPD, MEMS, and PV fabs, featuring a free blog (www.betasights.net). Starting with a degree in Materials Science and Engineering from MIT, he was a process engineer in IC, LED, and MEMS fabs, and developed custom tools and recipes. He managed applications and products for semiconductor OEMs from start-ups to stalwarts, and directed international JVs. As an award-winning technical editor for Solid State Technology, he wrote the popular weekly blog Ed’s Threads in 2006-2008. He is a member of the Materials Research Society. (Ref: http://www.linkedin.com/pub/ed-korczynski/2/345/19a)

1:30-2:00 Plasma diagnostics using harmonics analysis in processing plasmas,
-ChinWook Chung, Department of Electrical and Computer Engineering, HanYang University
Abstract: When a sinusoidal voltage is applied on a probe at a probe potential, the current flowing through the probe has many harmonics due to the nonlinearity of sheath. From the harmonic current components, plasma densities, electron temperatures, negative ion densities and negative ion temperature can be found. There are many advantages of this method such as relative low voltages (a few V), good time resolution (~msec), no perturbation (no net current), immune to rf interference, strong to contamination on probes. In this presentation, plasma measurements in various processing plasmas (SF6, CF4, N2, Ar, SiH4 etc) as well as relevant physics will be given. Also, a wafer type probe array for 2D plasma density profile measurement was developed and 2D plasma density profiles in various conditions will be presented.
Biography: TBD

2:00-2:30 Design specific variation in via/contact pattern transfer-Full chip analysis,
-Valeriy Sukharev, Jun-Ho Choy, Ara Markosian, Armen Kteyan and Yuri Granik, Mentor Graphics Corp.; Vladimir Bliznetsov, Institute of Microelectronics, 117685 Singapore
Abstract:  A novel model-based algorithm provides a capability to control full-chip design specific variation in pattern transfer caused by via/contact etch processes. This physics based algorithm is capable of detecting and reporting hotspots based on the fab defined thresholds of acceptable variations in critical dimension (CD) of etched shapes. It can be used also as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design. A realistic set of process parameters employed by the developed model allows using this novel via-contact etch (VCE) electronic design automation tool for the design aware process optimization in addition to the “standard” process aware design optimization. Measurements of the post-etch geometries of contact holes etched in the organosilicate glass (OSG) with fluorocarbon plasma (C4F8/N2/Ar) are used for model validation and calibration.
Biography: Dr. Sukharev received the M.S. degree in solid-state physics from the Moscow Institute of Electronic Technology (Technical University), Russia, and the Ph.D. degree in physical chemistry from the Karpov Institute of Physical Chemistry, Moscow, Russia. He has held various academic positions at the Karpov Institute of Physical Chemistry. He was a Visiting Professor with Brown University, Providence, RI, and a Guest Researcher with the National Institute of Standards and Technology (NIST), Gaithersburg, MD working on the physical chemistry of heterogeneous process. He held senior technical positions at LSI Logic Advanced Development Lab, Milpitas, CA working on modeling and simulating problems in microelectronics engineering. Since 2008, he is with Mentor Graphics Corporation, San Jose, CA, as part of the Ponte Solutions acquisition, where he was a Chief Scientist. He is the author and coauthor of more than 100 scientific publications, one book, and three book chapters and the holder of 20 plus U.S. patents. He served as a section chairman and a member of the program committees at many national and international conferences and as a reviewer for a number of profiling journals. His major research activity is related to the development of new full-chip modeling and simulation capabilities for the semiconductor processing and DFM applications.

2:30-3:00 Trends in Plasma Etching and Deposition for LED Fabrication,-David Lishan, Ph.D., Plasma-Therm LLC
Abstract: Plasma etching and deposition processes used in the fabrication of LEDs provide many challenges not found in mainstream silicon device production. Rapid market growth in a relatively new technology has resulted in constantly changing and diverse process requirements among the many LED device manufacturers. Fortunately, flexible processes, control technology and platforms are available to address the wide range of materials and substrate sizes used in various production strategies.
Biography: David Lishan received his Bachelor’s degree in Chemistry from UC, Santa Cruz and Ph.D. from UC, Santa Barbara in Solid State Electrical Engineering. During his career he worked on a wide range of chemistry, semiconductor, and materials R&D projects. He joined Plasma-Therm 11 years ago and currently holds the positions of Principle Scientist and Director of Technical Marketing. His interests are in the application of plasma processing for MEMS, nanotechnology, LEDs, thin film heads, and compound semiconductor applications.

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For details please contact Heather Korff, NCCAVS Office, 530-896-0477, heather@avs.org.