FREE ADMISSION - NO NEED TO REGISTER, JUST SHOW UP!!
Topic: 3D Packaging
Date: June 09, 2016
Time: 12:30 - 4:15pm
Free Lunch Sponsored by Kurt J. Lesker Company beginning at 12:30PM
Coffee Break Sponsored by UC Components beginning at 2:20PM
Presentations begin at 1:15PM
This meeting focuses on technologies and applications related to 3D Packaging. The purpose of this meeting is to bring together leading researchers in academia, government, and industry with innovative technologies to nurture a free exchange of triumphs and challenges in the advances in 3D Packaging applications.
1:15 - 1:20 Welcome
1:20 - 1:50 Novel Process of RDL formation for Advanced Packaging by Excimer Laser Ablation,
Markus Arendt, SUSS MicroTec Photonic Systems Inc.
Abstract: The continuous trend of the miniaturization, increasing performance and mobility of electronic devices drive the requirements of both, the chip itself, and its package type. The current integration process based on photolithography is facing several challenges to develop cost effective and innovative package designs that meet market's requirements. In support of this technology trend and to address the current photolithography process integration challenges, Excimer laser ablation is introduced to the semiconductor packaging industry as a disruptive patterning technology, using proven industrialized Excimer laser sources that emit high energy pulses at short wavelengths to remove materials, with almost no heat affection. The combination of the high-power Excimer laser source, large-field laser masks and precision projection optics enables the accurate replication and placement of fine resolution circuit patterns without all the disadvantages of wet-processing. With this type of patterning technology the industry gets cost effective access to non-photo sensitive materials, allowing for enhancements in chip or package performance. A new process is proposed, based on the front end of line dual damascene integration flow for building multilayer embedded RDL for Advanced Packaging using Excimer laser ablation. The new process uses Excimer laser ablation as the critical method to integrate via and RDL traces in one patterning process step, followed by seed layer deposition, plating, and standard planarization processes. The new proposed integration flow is explained in detailed, and its technical robustness for the chip interconnects combined with its commercial benefits to users is demonstrated. Also, the capability of this Excimer laser process to extend the material selection to non-photo materials is covered.
Bio: Dr. Markus Arendt is President of SUSS MicroTec Photonic Systems, an equipment supplier for lithography solutions for Advanced Packaging, 3D Integration, and MEMS industries. Throughout his 10 years with SUSS MicroTec, he has held a range of senior-level positions, from Division Head for the Photomask Equipment Division to VP of Operations. Previously, he was General Manager of ANKA Synchrotron Radiation Source, and responsible for the commercialization of products and services with Synchrotron Radiation. Markus holds a Diploma in Engineering from the University of Karlsruhe/Germany, and a Ph.D. in Economics from the University of Heidelberg/Germany.
1:50 - 2:20 Fun times in multi-die integration: Thin, small, 2D, 3D and in-between,
Sesh Ramaswami, Applied Materials Inc.
Abstract: It seems like every other day, we hear about instances where similar and dis-similar die are being integrated to deliver new end-application functionality at various price points. Even more are in the cards, as die will be physically partitioned, manufactured at their appropriate nodes and then brought back together. In the supply chain ecosystem, the high-end PCB's, high end flip chip substrates and wafer level Cu RDL traces are facing what seem like similar problems in polymer-metal interactions. At the die level, there is a need to go thin as well as go with narrow kerf where possible. This drives inflection in dicing/singulation technology, which is by no means trivial. This talk will provide a structure and context to the above topics and will be set up so to encourage a dialog with those in the audience who may be experts in the topic as well as those who are curious about it and would wish to learn more about the same.
Bio: Sesh Ramaswami is in Advanced Products Technology Development at Applied Materials responsible for identifying emerging requirements / industry challenges and developing new capability in multi-die packaging and devices that are being increasingly being categorized in the More-Than-Moore space. He is a co-author and contributor of a book published by McGraw Hill, entitled 3-D IC Stacking Technology. Sesh has over 31 years of semiconductor industry experience, with the last 20 at Applied Materials. Prior to Applied Materials, Sesh was at Advanced Micro Devices and National Semiconductor. A holder of thirty-eight U.S. patents, Sesh has undergraduate and graduate degrees in chemical engineering from Indian Institute of Technology, Kanpur, and Syracuse University, respectively, and an MBA.
2:20 - 2:40 Coffee Break and Networking
2:40 - 3:10 Optical Metrology and Inspection for Fan-Out Wafer Level Packaging (FOWLP),
Ben Garland, Jim Xu, Ph.D., and Vamsi Velidandla , Zeta Instruments Inc.
Abstract: Fan-Out Wafer Level Packaging (FOWLP) technology provides a cost effective solution for semiconductor devices requiring a smaller package footprint with higher input / output (I/O) along with improved thermal and electrical performance. Compared to conventional wafer level packaging, FOWLP presents tough challenges to traditional optical metrology and inspection tools due to a higher degree of wafer warpage, small RDL critical dimensions, and low reflectivity of epoxy mold compound (EMC). In this presentation, we will describe a unique optical metrology and inspection solution developed by Zeta Instruments and demonstrate its effectiveness on challenging FOWLP applications such as 2um RDL profiling, polyimide thickness measurement over black EMC, and defect inspection on carrier glass substrate and on EMC. The multi-mode approach to metrology allows the measurement of film thickness, step height, CD and roughness in the same tool. This reduces the yield loss from handling and contamination when using multiple tools. A multi-mode tool also reduces the overall metrology cost of the backend fab. In the past few years, the world's leading Foundry and OSATs have adopted the Zeta solution for their most advanced FOWLP process lines.
Bio: Ben Garland has over 19 years of technical sales & management experience. Prior to joining Zeta Instruments in 2009, he was a Sales Engineer and Area Technical Manager for Thermo Fisher Scientific, formerly Nicolet where he was a successful solutions provider responsible for the sales of the Nicolet branded spectroscopy systems. These products included both micro & macro FTIR, Raman & NIR spectrometer systems serving customers in the semiconductor, electronics, biotech, university, government, solar, aerospace, & pharmaceutical industries. He was also a member of Thermo's elite "taste-makers" group to help test, develop, and market new spectroscopy products. He has a MS degree in chemistry from the University of Utah and a BS degree in chemistry with a minor in physics from Idaho State University.
3:10 - 3:40 CMP for Advanced Packaging, Robert L. Rhoades, Entrepix, Inc.
Abstract: Chemical mechanical polishing (CMP) is the process that has enabled critical topography control in the most advanced semiconductor device designs since before the 0.25um node in the late 1990's. This process has been both praised for what it can achieve and cursed for difficulty and cost. As technology continues to evolve, many technology teams are now looking for increasingly creative ways to fabricate advanced packaging designs. The process specs for these applications are not nearly as stringent as, for example, sub-32nm FINFET gate formation, but packaging carries its own unique blend of requirements. Deposited films for these applications are typically much thicker than films in standard CMOS, thus CMP requires customization and process development often utilizing new pads or customized slurries for higher removal rates. In addition, some integrations require polishing of new materials for specialized purposes, such as refractory metals or unique polymers. Many other aspects of packaging applications represent challenges for CMP, including throughput, rapidly changing design rules, overall yield, and one of the biggest challenges of all - cost. This presentation will provide an overview of CMP for packaging and provide a few examples of issues encountered in developing this technology.
Bio: Robert Rhoades is the Chief Technology Officer for Entrepix, Inc.. He has been a recognized industry leader in CMP for over 21 years. In 2002, he joined Entrepix to launch a process foundry to provide CMP services for R&D prototypes through volume production on virtually any material and any wafer size. Dr. Rhoades earned B.S., M.S. and Ph.D. degrees in Electrical Engineering from the University of Illinois. He is a named inventor on roughly a dozen patents and has authored more than 90 technical publications and conference presentations.
3:40 - 4:10 Between 2D and 3D: WLFO Packaging Technologies and Applications,
Minghao Shen, Altera Corporation (now part of Intel)
Abstract: Given the growing challenge of following the Moore's Law, the semiconductor industry has been exploring various packaging solutions to further expand the performance and functionality of Si by SiP. Besides the well-known Si interposer base 2.5D, and 3D memory stacks, WLFO has been the leading solution of multi-die integration in many domains. The talk will discuss some of most promising WLFO and WLFO-like technologies with performance and cost comparison. I will go on to illustrate the concept of Si-interposer- substrate co-design, by utilizing high density bumping and interconnect, which blurs the boundary of front-end-of-line and far back-end-of-line, and enables true die segregation.
Bio: Dr. Minghao Shen is Principal packaging R&D engineer at Altera, now part of Intel. Ms. Shen received her BS in Physics at Beijing University, China, and PhD in Physics at Yale University. Prior to Intel, she worked at AMD / Spansion and Maxim Integrated as process R&D integration engineer. Her work expands from silicon Cu back end of line, TSV, and far back end of line process. With her wide span of semiconductor process development knowledge, she is leading the multi-die wafer level and panel level integration development at Altera.
All presentations will be requested to be posted on the TFUG and CMPUG Proceedings webpage.