SEMI Global Headquarters
Seminar rooms 1 & 2, 3081 Zanker Road, San Jose, CA 95134
**Park in front or behind the vacant building across from SEMI**
||Hok-Kin Choi, Intel, Hokkin.firstname.lastname@example.org
Sing-Pin Tay, AVS, email@example.com
Kapila Wijekoon, AMAT, firstname.lastname@example.org
Valeriy Sukharev, Mentor Graphics, Valeriy_sukharev@mentor.com
Lucia Feng, email@example.com
12:30 - FREE LUNCH - Sponsored by Kurt J. Lesker Company
1:15 - 1:20 Welcome
1:20 - 1:45 The Business Aspect of WLP Polymers
- Chris Blatt, TECHCET CA, LLC.
The WLP industry has been stable over the last several years with PI being the dominate player and no reason to change by the users. However, recent technology changes due to the internet of things and wearable technology trends, have created the need for new materials for this market. The business potential of this will be explored as well as projections for future growth.
1:45 - 2:35 Enabling Multi-Die Integration Through Advanced Packaging
- Sesh Ramaswami, Packaging Technologies, Advanced Product Technology Development, Silicon Systems Group, Applied Materials Inc.
The industry is seeking to increasingly leverage packaging technologies to deliver system level benefits (and hence differentiation) in performance, form factor, time to market and price. This talk will be anchored on issues and solutions from a process integration and equipment perspective.
2:35 - 2:55 Break and Networking
2:55 - 3:45 Electromigration Simulation Flow For Chip-Scale Parametric Failure Analysis
- Jun-Ho Choy, Mentor Graphics Corp.
A novel methodology for 3D IC full-chip power and ground nets redundancy-aware EM assessment based on IR-drop analysis was developed. Physics-based model for temperature- and residual stress-aware void nucleation and growth was developed and implemented in the flow. A developed technique for calculating the hydrostatic stress distribution inside a multi branch interconnect tree allows to avoid over optimistic prediction of the time to failure made with the Blech-Black analysis of individual branches of interconnect segment.
Jun-Ho Choy is an active R&D engineer of Mentor Graphics Corp., Fremont, CA. He received the B.S. degree at Seoul National University, Korea, M.S. at Sung Kyun Kwan University, Korea, and Ph.D. at Michigan Technological University, Houghton, MI, all in the field of Metallurgical & Materials Engineering. In semiconductor industry, he held the position of Device Engineer in Memory R&D Division at LG Semiconductor, Inc. Korea (later acquired by Hynix Semiconductor, Inc.), where he was actively engaged in the process development that improves device reliability. He also worked for LSI Logic Corp, Milpitas, CA, as a Principal Engineer developing physics-based electromigration simulator. Subsequently, he joined Ponte Solutions, Inc.(later acquired by Mentor Graphics), and participated in the development of physics-based plasma etching model. Jun-Ho’s research area also covers the modeling and simulation of interface instabilities, and electromigration of IC metallization.
3:45 - 4:35 The High Rise Chip: Monolithic 3D Integration of Logic and Memory
- Max M. Shulaker, Stanford University, CA
To meet the growing demand for improved information-technology (IT) systems, both the energy efficiency and computing power of digital logic systems must be drastically improved. While advances with conventional silicon CMOS continue to be made, alternative technologies are currently being explored. One such promising emerging nanotechnology is carbon nanotube (CNT) field-effect transistors (CNFETs); CNFET-based very-large-scale integrated (VLSI) digital systems are projected to improve the energy-delay product (EDP), a metric of energy efficiency, by an order of magnitude vs. silicon CMOS. Although such emerging nanotechnologies promise energy-efficient digital logic, it is important to note that IT applications increasingly rely on big-data analytics performed on data with massive volume and rate (i.e. abundant data applications). Therefore, solely increasing transistor performance will not translate to the required increases in system and application performance, as the latter will remain severely constrained by the growing memory-logic communication bottleneck. Rather, these emerging devices must be used in tandem with revolutionary digital system architectures (with fine-grained integration of logic circuits and massive amounts of memory) to meet the needs of future abundant data applications. Specifically, monolithic three-dimensional (3D) integration, whereby logic and memory layers are fabricated directly over previously fabricated layers on the same starting substrate, can achieve such increased levels of integration. In today’s talk, I will discuss how monolithic 3D integration is naturally enabled by emerging nanotechnologies for both logic and memory: particularly, CNFETs for logic circuits, and emerging non-volatile memory (NVM) technologies such as Resistive RAM (RRAM). Using such as integration scheme, I will demonstrate, for the first time, such monolithically-integrated 3D ICs, with arbitrary vertical interleaving layers of logic and memory.
Max Shulaker is a PhD candidate in Electrical Engineering at Stanford University, under the supervision of Professor Subhasish Mitra. He received his B.S. from Stanford University in Electrical Engineering. Max’s current research interests are in the broad area of nanosystems. His research results include the demonstration of the first carbon nanotube computer (highlighted on the cover of Nature, Sept. 2013), the first digital sub-systems built entirely using carbon nanotube FETs (awarded the ISSCC Jack Raper Award for Outstanding Technology-Directions Paper, 2013), the first monolithically-integrated 3D integrated circuits combining arbitrary vertical stacking of logic and memory (IEDM 2014), and the highest-performance CNFETs to-date (IEDM 2014). He is a Fannie and John Hertz Fellow and a Stanford Graduate Fellow.
All presentations will be requested to be posted on the CMPUG, PAG and TFUG Proceedings webpages.
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