Topic: Advanced FEOL Integration
Meeting Date: August 20 , 2008
Time: 2:00pm - 5:00pm

Agenda:
2:00 – 2:05pm Welcome/Introduction
2:05 - 3:10pm Presentations
3:10 – 3:25 pm Refreshments
3:25 – 5:00pm Presentations

Presentations:
2:00 – 2:05 Welcome/Introduction

2:05 – 2:40 Phase Change Memory: A Memory Technology for All Applications
- Dr. Stefan Lai, Vice President, Business Development, Ovonyx, Inc.
The growth of battery-powered, portable entertainment and communications applications has fueled a huge and increasing demand for low-power nonvolatile memory storage. This is currently being met with stored-charge NAND and NOR Flash memory, but clear scaling limits are approaching. Many alternative nonvolatile memories are being investigated, but, among these, phase-change technology is receiving the greatest attention and it is widely regarded as the most promising. Phasechange memory is being considered not only as a Flash memory replacement, but for development of a memory for multiple applications. The advantages of phase-change technology in addressing these new and emerging markets, the current status of phasechange memory commercialization, and the challenges it will face going forward will be reviewed.

Stefan K. Lai received his B.S. in applied physics from California Institute of Technology, and his Ph.D. in applied quantum physics from Yale University. From Yale, Dr. Lai joined IBM Yorktown TJ Watson Research Center as a Member of Technical Staff where he conducted research on silicon-silicon dioxide interface properties. Dr. Lai joined Intel in 1982 to develop scalable E2PROM and he co-invented the EPROM tunnel oxide (ETOX) flash memory cell, which has become industry standard. He and his team have developed through 2006 ten generations of ETOX technologies achieving 1000X cell size reduction. In 1999, he started a team to develop alternative memory technologies and Intel was one of first major semiconductor company to pursue phase change memory (PCM). He was appointed Vice President of Intel’s Technology and Manufacturing Group in 2000. He retired from Intel end of 2006. Currently, he is Vice President, Business Development, Ovonyx Inc. Dr. Lai was recognized as an IEEE Fellow in 1998 for his research on the properties of silicon MOS interfaces and the development of flash EPROM memory. He is also awarded the 2008 IEEE Andrew Grove Award for his contribution to flash memories.

2:40 – 3:10 Advanced Activation Using Various Thermal Budget Regimes Such As Flash, Multiple Flashes And Flash + Spike Annealing
- J. Gelpey, W. Lerch, S. Paul, J. Niess, S. McCoy, Mattson Technology Inc.
Millisecond annealing as an equipment technology provides ultra-sharp temperature peaks which favors dopant activation but nearly eliminates dopant diffusion to form extremely shallow highly electrically-activated junctions. On boron and arsenic beamline implanted wafers the formation of ultra-shallow junctions at peak temperatures ranging from 1250°C to 1300°C was investigated followed by a spike anneal. The subsequent spike anneal temperature is in the range of 900°C to 1000°C. Multiple ms anneal process have been performed to reduce the sheet resistance. Furthermore the standard flash anneal condition of a 750°C intermediate temperature followed by the flash is changed to a high intermediate temperature of 950°C followed by a flash anneal up to 1300°C. All these annealing schemes will be analyzed through four point probe measurement. Selected samples were analyzed by Hall-effect for peak activation, and by Secondary Ion Mass Spectrometry for profile shape as well as diffusion. Transmission electron microscopy was used to study remaining defects. Finally selected boron and arsenic dopant profiles are compared to predictive simulation results which address the diffusion and activation at extrinsic concentrations. Integration implications of the ms anneal process are also discussed.

Jeff Gelpey is currently a Fellow at Mattson Technology, Inc. working mostly on Mattson’s Millios™ ms annealing technology. He holds an MSEE and BSEE from MIT in the area of solid state physics. Mr. Gelpey started working as a process engineer for III-V and II-VI semiconductors at Honeywell. In 1981 he moved to the field of semiconductor processing equipment with work at Eaton (now Axcelis) on ion implantation and rapid thermal processing. He has worked in the RTP field for over 25 years at Mattson and its predecessor companies (Vortek, STEAG, AST Elektronik) as well as at Peak Systems and Eaton. His roles have involved equipment design, process development and marketing. Mr. Gelpey is mostly involved in the development and bringing to market an advanced milli-second annealing tool for ultra-shallow junction formation. He has been an MRS member since 1981 and has organized several symposia for MRS, ECS and the IEEE RTP Conference.

3:10 – 3:25 BREAK

3:25 – 4:00 Stress engineering and its interactions with high-k/metal gate and USJs
- Dr. Victor Moroz, Principal Engineer, Synopsys, Inc.
Stress engineering has become an indispensable enabler of semiconductor applications, used to boost performance or suppress leakage or both. Besides the intentional stress sources there are several major unintentional stresses arising during the manufacturing steps, some appearing temporarily, whereas others making a permanent impact on the transistors. The cocktail implants that are commonly utilized for USJ optimization exhibit strong interaction with lattice stress. The introduction of high-k/metal gate stacks makes a major impact on the stress engineering techniques, with the combination raising reliability concerns. Considering that stress propagates about 2 microns in silicon, the layout scaling brings an increasing number of neighbors affecting performance of each transistor, which disturbs performance and functionality of the chip. This talk reviews some of these trends and provides a modeling perspective.

Dr. Victor Moroz received his Ph.D. in Semiconductor Physics in 1992 from the University of Nizhny Novgorod, Russia. His professional career revolves around semiconductor physics and includes silicon process integration in the industry, teaching undergraduate and graduate students, and for the last 14 years - developing process simulation and DFM tools at TMA and TCAD Department at Synopsys. Several facets of this activity are reflected in 70+ technical papers and 10+ patents.

4:00 – 4:30 Leakage Monitoring and Control with an Advanced e-Beam Inspection System
- Hong Xiao and Jack Jau, Hermes Microvision, Inc., San Jose, CA, USA, Hermes Liu, J H Yeh, Chan Lon Yang, S C Lei, J Y Kao, Y D Yang, Mingsheng Tsai, S F Tzou, Central R&D Division, United Microelectronics Corp., Taiwan, ROC
Junction leakage control is studied with electron beam (e-beam) defect inspection after tungsten chemical mechanical polishing (WCMP). Leakage-induced bright voltage contrast (BVC) defects are detected. For both wafer to wafer (WtW) and within wafer (WiW), e-beam inspection results strongly correlate with leakage results of wafer acceptance test (WAT). Failure analysis results showed that the junction leakage was caused by lateral diffusion of nickel silicide (NiSi) underneath the spacer. The extrusion length correlates with gray levels of the tungsten plug very well. In this study we found the optimized condition to suppress junction leakage and also confirmed that post WCMP e-beam inspection can be used to monitor and control junction leakage.

Dr. Hong Xiao is a technical marketing specialist at Hermes-Microvision, Inc., a provider of semiconductor inspection solutions. Previously, he was a senior process engineer in Motorola Semiconductor Production Sector, and an associate professor of Austin Community College(ACC) in Semiconductor Manufacturing Technology program. After receiving the Ph.D., Dr. Xiao worked at Applied Materials as senior technical instructor in Technical Training, with expertise in dielectric thin film deposition, semiconductor process integration and plasma physics. From fall 1998 to fall 2000, he taught in ACC, and also developed the professional training materials of semiconductor processing technology. Dr. Xiao is the author of over 20 academic papers and a textbook, “Introduction to Semiconductor Manufacturing Technology”, published by Prentice Hall.

4:30 – 5:00 Multi-Gate MOSFETs: Front-End Materials and Process Needs
- Prof. Tsu-Jae King Liu, University of California, Berkeley
Suppression of leakage current and reduction in device-to-device variability will be key challenges for sub-45nm CMOS technologies. This talk will discuss FEOL process and materials requirements for scaling CMOS technology to the end of the roadmap.

Prof. Tsu-Jae King Liu received a B.S., M.S. and Ph.D. degrees in Electrical Engineering from Stanford University. She joined the Xerox Palo Alto Research Center as a Member of Research Staff in 1992, to research and develop polycrystalline-silicon thin-film transistor technologies for flat-panel display applications. In August 1996 she joined the faculty of the University of California at Berkeley, where she is now Professor of Electrical Engineering and Computer Sciences (EECS) and Associate Dean for Research in the College of Engineering. Her research activities are presently in nanometer-scale logic and memory devices and technology. Her awards include the DARPA Significant Technical Achievement Award (2000) for development of the FinFET. She has authored or co-authored over 300 publications and patents, and is an IEEE Fellow.

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